#include <stdint.h>

#if defined(__ARMCC_VERSION)
  #if (__ARMCC_VERSION >= 6010050)
  #else
    #pragma anon_unions
  #endif
#endif  
  
#undef __IM
#undef __IOM
#undef __OM

#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
    
typedef struct
{
    struct {
        __IM uint32_t ro0004_Revision:4;
        __IM uint32_t ro0412_PartNum:12;
        __IM uint32_t ro1604_Architecture:4; // F=V7, C=V6
        __IM uint32_t ro2004_Variant:4;
        __IM uint32_t ro2408_Impl_0x41:8;
    }CPUID;
    struct {
        __IOM uint32_t rw0009_VectActive:9;
        __IOM uint32_t zz0902_rsvd1:2;
        __IOM uint32_t ro1101_RetToBase:1;
        __IOM uint32_t ro1209_VectPending:9;
        __IOM uint32_t zz2102_rsvd2:2;
        __IOM uint32_t ro2301_ISRPending:1;
        __IOM uint32_t ro2401_ISRPreempt:1;
        __IOM uint32_t wo2501_PendSTClr:1;
        __IOM uint32_t rw2601_PendSTSet:1;
        __IOM uint32_t wo2701_PendSvClr:1;
        __IOM uint32_t rw2801_PendSvSet:1;
        __IOM uint32_t zz2902_rsvd3:2;
        __IOM uint32_t wo3101_NMIPendSet:1;
    }ICSR;
    struct {
        __IOM uint32_t zz0008_Pad0:8;
        __IOM uint32_t rw0824_VTOR:24;
    }VTOR;
    union {
        uint32_t val32;
        struct {
        __OM uint32_t wo0001_VectResetReq:1;
        __OM uint32_t wo0101_VectClearActive:1;
        __OM uint32_t wo0201_SysResetReq:1;
        __IM uint32_t zz0305_Rsvd1:5;
        __IOM uint32_t rw0803_PriGroup:3; // 7:1/6:2/../0:7
        __IM uint32_t zz1104_Rsvd2:4;
        __IOM uint32_t rw1501_BigEndian:1;
        __IOM uint32_t rw1616_VectKey_w05FA_rFA05:16;
        };
    }AIRCR;
    struct {
        __IM uint32_t zz0001_:1;
        __IOM uint32_t rw0101_SleepOnExit:1;
        __IOM uint32_t rw0201_SleepDeep:1;
        __IOM uint32_t zz0301_:1;
        __IOM uint32_t rw0401_SevOnPend:1;
        __IM uint32_t zz0527_:27;
    }SCR;
    struct {
        __IOM uint32_t rw0001_NonBaseThrdEna:1;
        __IOM uint32_t rw0101_UserSetMPend_AllowUserSetPendIRQInSTIR:1;
        __IM uint32_t zz0201_:1;
        __IOM uint32_t rw0301_Unalign_Trap:1;
        __IOM uint32_t rw0401_Div_0_Trp:1;
        __IM uint32_t zz0503_:3;
        __IOM uint32_t rw0801_NmiHftIgnrPreciseBFt:1;
        __IOM uint32_t rw0901_StkAlign:1;
        __IM uint32_t zz1006_:6;
        __IOM uint32_t rw1601_EnDCache:1;
        __IOM uint32_t rw1701_EnICacheC:1;
        __IOM uint32_t rw1801_EnBranchPredict:1;
        __IM uint32_t rw1913_:13;        
    }CCR;
    
    union {
        __IOM uint8_t  ary8[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
        __IOM uint32_t  ary32[12U / 4];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
        struct {
            __IOM uint8_t SHPR_MemManageFault;
            __IOM uint8_t SHPR_BusFault;
            __IOM uint8_t SHPR_UsageFault;
            __IOM uint8_t SHPR_pads1[4];
            __IOM uint8_t SHPR_SVC;
            __IOM uint8_t SHPR_DebugMon;
            __IOM uint8_t SHPR_pads2;
            __IOM uint8_t SHPR_PendSv;
            __IOM uint8_t SHPR_SysTick;
        };
    }SHPR;
  
    struct {
        __IOM uint32_t ro0001_MemFaultAct:1;
        __IOM uint32_t ro0101_BusFaultAct:1;
        __IOM uint32_t zz0201_:1;
        __IOM uint32_t ro0301_UsgFaultAct:1;
        __IOM uint32_t zz0403_:3;
        __IOM uint32_t ro0701_SvCallAct:1;
        __IOM uint32_t ro0801_MonitorAct:1;
        __IOM uint32_t zz0901_:1;
        __IOM uint32_t ro1001_PendSvAct:1;
        __IOM uint32_t ro1101_SysTickAct:1;
        __IOM uint32_t ro1201_UsgFaultPended:1;
        __IOM uint32_t ro1301_MemFaultPended:1;
        __IOM uint32_t ro1401_BusFaultPended:1;
        __IOM uint32_t ro1501_SvCallPended:1;
        __IOM uint32_t rw1601_MemFaultEna:1;
        __IOM uint32_t rw1701_BusFaultEna:1;
        __IOM uint32_t rw1801_UsgFaultEna:1;
        __IOM uint32_t zz1913:13;
    }SHCSR;
    
    struct {
        __IOM uint32_t rw1c0001_IAccViol:1;
        __IOM uint32_t rw1c0101_DAccViol:1;
        __IOM uint32_t zz0201_:1;
        __IOM uint32_t rw1c0301_MUnStkErr:1;
        __IOM uint32_t rw1c0401_MStkErr:1;
        __IOM uint32_t rw1c0501_MLSPErr_LazyStatePreserve:1;
        __IOM uint32_t zz0601_:1;
        __IOM uint32_t rw1c0701_MMARValid:1;
        
        __IOM uint32_t rw1c0801_IBusErr:1;
        __IOM uint32_t rw1c0901_PreciseErr:1;
        __IOM uint32_t rw1c1001_ImpreciseErr:1;
        __IOM uint32_t rw1c1101_UnStkErr:1;
        __IOM uint32_t rw1c1201_StkErr:1;
        __IOM uint32_t rw1c1301_LSPErr_LazyStatePreserve:1;
        __IOM uint32_t zz1401_:1;
        __IOM uint32_t rw1c1501_BFARValid:1;
        
        __IOM uint32_t rw1c1601_UndefInstr:1;
        __IOM uint32_t rw1c1701_InvState:1;
        __IOM uint32_t rw1c1801_InvPC:1;
        __IOM uint32_t rw1c1901_NoCP:1;
        __IOM uint32_t zz2004_:4;
        __IOM uint32_t rw1c2401_Unaligned:1;
        __IOM uint32_t rw1c2501_DivByZero:1;
        __IOM uint32_t zz2606_:6;        
    }CFSR;
    
    struct {
        __IM uint32_t zz0001_:1;
        __IOM uint32_t rw1c0101_VectTbl_readFault:1;
        __IM uint32_t zz0228_:28;
        __IOM uint32_t rw1c3001_Forced:1;
        __IOM uint32_t rw3101_DebugEvent_WhenHaltDis:1;
    }HFSR; // offset: 0x02C
    
  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
   __IM uint32_t omits[14];
    //----------------------cache-----------------------------
    struct {
        __IM uint32_t ro0003_L1Type:3; // no/I/D/I+D
        __IM uint32_t zz0321_:21;
        __IM uint32_t ro2403_LvOfCoherency:3;  // 1=IorD
        __IM uint32_t ro2703_LvOfUnification:3; // 1=IorD
        __IM uint32_t zz3002_:2;
    } CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
    struct {
        __IM uint32_t ro0004_IMinLine:4;
        __IM uint32_t zz0410_0:10;
        __IM uint32_t ro1402_1:2;
        __IM uint32_t ro1604_DMinLine:4;
        __IM uint32_t ro2004_ExAccessGranulity_4_8_16_etc:4;
        __IM uint32_t ro2404_CWG_na_8_16_32_etc:4;
        __IM uint32_t zz2804_:4;
    } CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
    struct {
        __IM uint32_t ro0003_LineSize_16_32_64:3;
        __IM uint32_t ro0309_Associativity:9;
        __IM uint32_t ro1201_Ways:1; // I$ 2way 512 sets ; D$ 4way 256 sets
        __IM uint32_t ro1315_NumSets:15;
        __IM uint32_t ro2801_HasWrAlc:1;
        __IM uint32_t ro2901_HasRdAlc:1;
        __IM uint32_t ro3001_HasWrBk:1;
        __IM uint32_t ro3101_HasWrTh:1;
    } CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
  
    struct {
        __IOM uint32_t rw0001_Select_IorD:1;
        __IOM uint32_t rw0103_Level_0IsL1:3;
        __IM uint32_t zz0428_:28;
    } CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
  
    struct {
        __IOM uint32_t rw0002_CP0:2;
        __IM uint32_t zz0218_:18;
        __IOM uint32_t rw2002_CP10_forFPU:2;
        __IOM uint32_t rw2202_CP11_forFPU:2;
        __IM uint32_t zz2408_:8;
    } CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
        uint32_t RESERVED3[93U];
  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
        uint32_t RESERVED4[15U];
  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
        uint32_t RESERVED5[1U];
  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
        uint32_t RESERVED6[1U];
  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
        uint32_t RESERVED7[6U];
  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
        uint32_t RESERVED8[1U];
  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
} MySCB_Type, SCBFine_t;